Qualcomm recently announced the creation of the world's first mass-market RISC-V Android System on a Chip (SoC) in partnership with Google. Google had previously declared official support for RISC-V in Android and laid out plans to make it an equivalent platform to Arm in terms of tier and importance. This collaboration with Qualcomm for hardware development sees the creation of a “RISC-V Snapdragon Wear” chip. While the chip is yet to be named officially, Qualcomm's global commercialization strategy includes a RISC-V-based wearables solution covering the United States.
The Relevance of RISC-V In the Mobile Architecture Landscape
The RISC-V architecture poses a significant threat to the Arm CPU architecture, the current leading processor architecture for mobile devices. One key advantage of the RISC-V architecture is its open-source nature, which makes it a more affordable and flexible option compared to the Arm architecture. This also allows companies to create fully open-source chips without incurring licensing fees, thus giving rise to competitions in Arm's chip-design business. The chips produced by the open-source foundation can cater to both proprietary and open needs. Furthermore, the volatility of Arm's business in recent years and conflicts relating to its acquisition of chip design firm Nuvia serve as reasons for seeking alternatives such as the RISC-V.
The Long Road Ahead For RISC-V SoC's
While Qualcomm and Google's recent venture is significant, it's worth noting that the RISC-V as a system CPU requires considerable effort to be a viable Android platform. Necessary development tools, such as Software Development Kits (SDKs), compilers, libraries, and more, need to embrace the new architecture. Google has a multitude of tasks ahead to ensure Android OS is compatible with RISC-V. However, the Android Runtime (ART) allows for applications written in Java (or Kotlin) to work efficiently on RISC-V code. Nevertheless, there are currently no details available about the commercial launch date of the revolutionary RISC-V wearable solution.