Taiwan Semiconductor Manufacturing Co., the world’s largest contract chip manufacturer, is preparing a different method for assembling the complex processors powering artificial intelligence, confirming it is nearing final specifications for “panel-level” packaging. This technique, aimed at chip designs from demanding customers like Nvidia and Google, ditches traditional round silicon wafers for square substrates, according to a report from Nikkei Asia.
The initial format will measure 310mm by 310mm, a move intended to pack more silicon into tighter spaces and boost computing performance for AI tasks, with TSMC targeting small-volume production around 2027.
The potential benefits of panel-level packaging (PLP) lie partly in manufacturing economics; processing larger rectangular panels can theoretically yield more final packages per substrate compared to round wafers, potentially reducing per-unit costs for certain chip types. However, this shift necessitates substantial adjustments across the semiconductor supply chain, requiring equipment makers and material suppliers to adapt to the square format.
It addresses a growing physical constraint: Nikkei Asia notes industry estimates suggest a standard 12-inch wafer fits only about 16 sets of Nvidia’s current B200 superchip packages. The larger surface area of panels is envisioned as a way to overcome this density limit for future AI systems.
Beyond Round Wafers: TSMC Bets on Panels for AI Scale
Developing this technology involves considerable technical difficulty. One of the main challenges, is achieving high-yield process uniformity—in deposition, etching, and lithography—across the larger, non-circular panel surface without defects or warping.
“It is particularly challenging to coat the whole substrate with chemicals evenly,” a person familiar with the development told Nikkei Asia, explaining why TSMC opted for a moderate initial panel size to manage quality. TSMC Chairman and CEO C.C. Wei had previously confirmed the company was working on panel-level chip packaging in mid-2024, suggesting at the time it would take about three years for the tech to be introduced. A pilot production line is currently being built in Taoyuan, Taiwan to refine these processes. Notably, TSMC explored collaborating with display manufacturers like Foxconn affiliate Innolux, who are experienced with rectangular formats, but ultimately opted to develop the technology alone due to the higher precision standards demanded by advanced chip packaging.
This focus on panel-level techniques complements TSMC’s existing, highly sought-after advanced packaging methods like CoWoS (Chip-on-Wafer-on-Substrate). CoWoS, which allows for the dense integration of different chiplets like GPUs, CPUs, and high-bandwidth memory (HBM), is already essential for current-generation AI accelerators and remains a critical technology for TSMC’s clients. Panel-level packaging represents a future step aimed at enabling even larger and more complex integrations as AI demands continue to scale.
Anchoring Advanced Tech Amid Global Expansion
TSMC’s decision to develop panel-level packaging primarily in Taiwan aligns with its long-standing strategy of keeping the most advanced research, development, and initial manufacturing close to home. This strategy persists despite a massive international expansion, highlighted by a recently confirmed $165 billion investment commitment in Arizona. The US project, backed by $6.6 billion in CHIPS Act grants and $5 billion in loans, includes multiple fabs and packaging facilities but will focus initially on established process nodes and packaging types. TSMC projects these US sites will account for only about 7% of its total output when complete.
This geographic balancing act is influenced by economics and strategy; producing chips in Arizona is expected to be roughly 10% more expensive than in Taiwan, reinforcing the economic logic of concentrating leading-edge work domestically. TSMC’s concurrent domestic expansion, including a new 2-nanometer fab in Kaohsiung set for production in late 2025, further demonstrates this Taiwan-centric approach for its newest capabilities.
Meeting the Insatiable Demand of AI Hardware
The fundamental driver for panel-level packaging is the exponential growth in computing power required by AI. Companies are increasingly seeking ways to pack more processing power into single modules. Leading AI companies are pushing hardware limits. OpenAI, for example, is developing its own custom AI chips, reportedly planning production with TSMC starting in 2026. This reflects a wider industry movement, with Meta, AWS, and Apple also developing proprietary silicon optimized for their specific AI workloads, reducing reliance on off-the-shelf components from suppliers like Nvidia. These efforts require sophisticated packaging solutions capable of integrating diverse chiplets, fueling the need for methods that offer greater density and performance than current wafer-based approaches allow.
Navigating a Complex Global Stage
TSMC operates within a tense geopolitical environment marked by the US-China tech rivalry. Washington has steadily expanded export controls targeting China’s access to advanced AI chips and semiconductor manufacturing technology. The U.S. government aims to limit perceived national security risks, with former Commerce Secretary Gina Raimondo stating last year regarding the technology’s dual-use nature: “The semiconductors that power artificial intelligence can be used by adversaries to run nuclear simulations, develop bio weapons, and advance their militaries.” These controls impact global supply chains and add layers of compliance complexity for TSMC.
Compounding these pressures, TSMC is currently facing a US Commerce Department investigation, reported April 8, 2025, over concerns that a chip it manufactured for an intermediary might have ended up in a blacklisted Chinese tech giant Huawei’s AI processor, potentially exposing the company to fines exceeding $1 billion and casting a shadow over its US operations and CHIPS Act funding. While TSMC states it complies with all regulations, the situation highlights the extreme sensitivity surrounding advanced AI hardware and the regulatory risks involved.
This environment likely encourages TSMC to keep pioneering techniques like panel-level packaging initially within Taiwan for maximum oversight. Meanwhile, competitors are not standing still; ASE Technology Group is actively developing its own panel-level solutions, and Huawei is pursuing panel-level technology with domestic partners like BOE as part of China’s drive for semiconductor self-sufficiency.
