The successful “bring up” signifies that the earliest Venice CCD samples are functional, passing basic validation tests. Achieving this on a completely new process node like TSMC’s N2 is particularly noteworthy, as it’s the foundry’s first to employ Gate-All-Around (GAA) nanosheet transistors. This transistor architecture succeeds FinFET designs and is engineered for improved performance and power efficiency scaling.
TSMC officially targets N2 to offer either a 15% speed increase at the same power level or a 24% to 35% power reduction compared to its N3 nodes, alongside a roughly 1.15x increase in logic density, leveraging its NanoFlex design-technology co-optimization (DTCO) framework. How these process-level improvements translate to the final Venice EPYC processors will depend on AMD’s Zen 6 design specifics and implementation choices.
AMD and TSMC Deepen Partnership on 2nm
Both companies emphasized their joint efforts. “TSMC has been a key partner for many years and our deep collaboration with their R&D and manufacturing teams has enabled AMD to consistently deliver leadership products that push the limits of high-performance computing,” stated Dr. Lisa Su, chair and CEO of AMD in a press release. “Being a lead HPC customer for TSMC’s N2 process and for TSMC Arizona Fab 21 are great examples of how we are working closely together to drive innovation and deliver the advanced technologies that will power the future of computing.”
TSMC Chairman and CEO Dr. C.C. Wei remarked in the AMD announcement, “We are proud to have AMD be a lead HPC customer for our advanced 2nm (N2) process technology and TSMC Arizona fab. By working together, we are driving significant technology scaling resulting in better performance, power efficiency and yields for high-performance silicon. We look forward to continuing to work closely with AMD to enable the next era of computing.”
AMD’s N2 progress comes as competitor Intel targets the first half of 2026 for its Xeon ‘Clearwater Forest’ processors, which will utilize its comparable 18A manufacturing technology.
Manufacturing Strategy and Trade Dynamics
Alongside the N2 development, AMD also revealed the successful validation of its current 5th Generation EPYC processors manufactured at TSMC’s Fab 21 facility in Arizona, affirming its commitment to U.S. manufacturing. This highlights AMD’s utilization of TSMC’s expanding US production footprint as part of a broader strategy. However, the location of manufacturing carries increasingly complex implications beyond logistics, particularly concerning international trade and geopolitical factors.
A recent shift in import regulations from China’s General Administration of Customs, effective April 11, 2025, illustrates these complexities. China now officially defines a semiconductor’s ‘country of origin’ as the location where the wafer is fabricated. This rule contrasts with those in the US, which often prioritize the location of final “substantial transformation,” such as packaging, in origin determinations.
Under these new Chinese rules, chips produced by TSMC, UMC, and other foundries within Taiwan—a territory China claims as its own—are set to be treated differently from those made in the USA when imported into China. While chips manufactured at TSMC’s Arizona fab could face tariffs as US-origin goods, those fabricated in Taiwan, including potentially the N2-based EPYC “Venice” CPUs, may bypass tariffs, regardless of AMD’s US headquarters.
This could give AMD, and other firms using Taiwanese fabs, a potential advantage in accessing the crucial China market, while potentially disadvantaging chipmakers relying primarily on fabs within the United States
