Semiconductor design company Synopsys, has unveiled a cutting-edge Ethernet blueprint with a 1.6 terabit (1.6T) capability, aimed specifically at powering artificial intelligence (AI) applications within datacenters. The company, headquartered in California and celebrated for its electronic design automation (EDA) tools, provides this latest innovation as the world’s first comprehensive 1.6T Ethernet intellectual property (IP) solution. This technology is designed to help chipmakers address the surging bandwidth requirements necessitated by the advancement of AI processing.
Designed for Future Demands
While the IEEE is slated to ratify the latest iteration of the 1.6 Tb Ethernet standard only by 2026, Synopsys asserts that its groundbreaking design equips manufacturers with the crucial IP needed to develop high-speed networking silicon today. The solution incorporates support for various Ethernet rates, including 4 x 400G, 2 x 800G, and 1.6T, facilitated through 112 Gbps and 224 Gbps SerDes. Additional components of the solution encompass 1.6T media access control (MAC) and physical coding sublayer (PCS) features, alongside 224G Ethernet PHY and verification IP, enabling a comprehensive suite for chip design.
The drastic uptick in AI-related activities, particularly in cloud datacenters, has significantly pressured existing data networks. This pressure is due to the immense data volumes required for AI model training, necessitating substantial enhancements in Ethernet speeds to keep up with the escalating demands.
Industry Embrace and Innovations
The Ethernet Alliance has expressed its support for Synopsys’ initiative. Peter Jones, the chairman of the Ethernet Alliance and a Distinguished Engineer at Cisco, underlined the importance of having robust development tools to support the next generation of Ethernet standards, especially to accommodate the increasing needs of large language modeling, high-performance computing (HPC) simulation, and AI training within hyperscale datacenters.
Synopsys highlights that its 1.6T Ethernet MAC and PCS components have been engineered to halve the required silicon area while cutting down latency by 40 percent, thanks to a patented Reed-Solomon Forward Error Correction architecture. The availability of these components, which are already being adopted by multiple customers, alongside the solution’s validation across various hardware platforms, PHYs, and Ethernet verification suites, promises to make significant strides in networking technology. This development denotes a key milestone in meeting the burgeoning network performance requirements prompted by the rapid advancement of AI technologies.
Last Updated on November 7, 2024 9:58 pm CET
